1. Field of the Invention
The present invention relates to nonvolatile memory arrays, and particularly to those memory arrays having resistive memory elements.
2. Description of the Related Art
A variety of memory array architectures are known that incorporate programmable resistors, variable resistors, switchable resistor elements, or other resistor elements whose resistance may be varied, or whose resistance may be changed from a high resistance to a low resistance state, and may be changed back to the high resistance state, to achieve a programmable and non-volatile memory array. Such memory array architectures have not been able to achieve the array density as other types of memory, such as NAND flash arrays. However, as memory technology continues to scale to smaller geometries, resistive memory cell technologies are increasingly advantageous.
Referring now to FIG. 1, a schematic diagram is shown of a memory array 200 known in the art. Three select lines 202, 204, 206 are shown, as well as two reference lines 213, 217 and four data lines 212, 214, 216, 218. Data lines 212, 214 and reference line 213 together form line set 208, and data lines 216, 218 and reference line 217 together form line set 210. The data lines are generally parallel to the reference lines, and both are generally perpendicular to the select lines. A total of twelve different memory cells are shown associated with various ones of these array lines. For example, memory cell 220 is associated with select line 204, data line 214, and reference line 213. The memory cell 220 includes a switchable resistor memory element 222 in series with a switch device 224, together coupled between the data line 214 and the reference line 213. Semiconductor structures implementing such a memory array 200 are described in U.S. Pat. No. 7,345,907 to Roy E. Scheuerlein, entitled “Apparatus and Method for Reading an Array of Nonvolatile Memory Cells Including Switchable Resistor Memory Elements.”
Referring now to FIG. 2, a schematic diagram is shown of a memory array 150 known in the art, which combines pairs of adjacent data lines described above into a single data line (bit line) which is used to access two memory cells. Three word lines (i.e., select lines) 172, 174, 176 are shown, as well as three sense lines 154, 158, 162 and three bit lines 152, 156, 160. Each memory cell includes a switchable resistor memory element in series with a switch device, together coupled between a sense line and a bit line. Such a memory array 150 is described in U.S. Pat. No. 6,801,448 to Sheng Teng Hsu, entitled “Common Bit/Common Source Line High Density 1T1R R-RAM Array.”